1. Technical Field
The present invention relates to a semiconductor memory device, and an electronic apparatus containing the same, and more specifically, a semiconductor memory device having a capacitor part using a ferroelectric film, or similar.
2. Related Art
Ferroelectric random access memory (FeRAM) devices, which store information by utilizing the hysteresis found between the polarization and electric field of ferroelectric material, have been gathering attention because of their high-speed operation, low power consumption and non-volatility.
Each of the ferroelectric memory cells constituting a memory cell array is connected to a word line and a plate line, which extend in a row direction, and also to a bit line, which extends in a column direction.
However, with the aforementioned configuration, when reading information from a selected cell, information in unselected memory cells in the same row as the selected memory cell will also appear on a bit line because the unselected memory cells are connected to the same word line and plate line as the selected memory cell. In addition, FeRAM reading is what is called destructive reading, and requires re-writing after reading. Accordingly, it is necessary to re-write data to not only the selected memory cell but also the memory cells in the same row as the selected memory cell.
Meanwhile, the ferroelectric material that constitutes a memory cell capacitor deteriorates as the number of information reads/writes increases. Reducing that deterioration is important for extending the life of ferroelectric random access memory.
As an example of related art, an article titled “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM” (IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, May 2002, p.p. 592-598) discloses a technique in which the plate lines change their displacements, forming in a step-like pattern, so that memory cells arranged in the same row direction do not connect with the same plate line.
As an example of related art, JP-A-2004-164730 discloses a technique in which four memory cells are connected to each plate line and word line in an 8-row by 8-column ferroelectric random access memory cell array to reduce the number of unnecessary accesses, reducing ferroelectric random access memory cell deterioration.